Vertical gallium nitride based fets with regrown source contacts

ABSTRACT

A transistor includes a III-nitride substrate, a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type, and a plurality of III-nitride fins on the first III-nitride layer, wherein each of the plurality of III-nitride fins is separated by one of a plurality of first recess regions and characterized by a fin surface, wherein the plurality of III-nitride fins are characterized by the first conductivity type. The transistor also includes a III-nitride gate layer having a second conductivity type opposite to the first conductivity type in the plurality of first recess regions, wherein a surface of the III-nitride gate layer is substantially coplanar with the fin surface, and a regrown III-nitride source contact portion coupled to each of the plurality of III-nitride fins, wherein the regrown III-nitride source contact portion is characterized by the first conductivity type.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.17/211,562, filed on Mar. 24, 2021, entitled “Method and System forRegrown Source Contacts for Vertical Gallium Nitride Based FETS,” whichclaims the benefit of priority to U.S. Provisional Patent ApplicationNo. 63/000,968, filed on Mar. 27, 2020, entitled “Method and System forRegrown Source Contacts for Vertical Gallium Nitride Based FETS,” thedisclosures of which are hereby incorporated by reference in theirentirety for all purposes.

BACKGROUND OF THE INVENTION

Power electronics are widely used in a variety of applications,including power conversion, electric motor drives, switching powersupplies, lighting, etc. Power electronic devices such as transistorsare commonly used in such power switching applications. The operation ofthe present generation of power transistor devices, particularly withhigh voltage (>600V) handling capability, is hampered by slow switchingspeeds, and high specific on-resistance.

Thus, there is a need in the art for power transistor devices exhibitinglow capacitance, a low, positive threshold voltage, and low specificon-resistance along with high breakdown voltage.

SUMMARY OF THE INVENTION

The present invention relates generally to vertical fin-based fieldeffect transistor (FET) devices with an improved combination of leakagecurrent, maximum electric field, and on-resistance for a given thresholdvoltage. Embodiments of the present invention provide novelvertical-fin-based FET devices and methods of fabricating such FETdevices with improved specific on-resistance, leakage current, andbreakdown voltage.

In one aspect of the present invention, a method for forming analignment contact includes: providing a III-nitride substrate;epitaxially growing a first III-nitride layer on the III-nitridesubstrate, wherein the first III-nitride layer is characterized by afirst conductivity type; forming a first hardmask layer on the firstIII-nitride layer; forming a plurality of III-nitride fins on the firstIII-nitride layer using the first hardmask layer as a mask, wherein eachthe plurality of III-nitride fins is separated by one of a plurality offirst recess regions, wherein the plurality of III-nitride fins arecharacterized by the first conductivity type; epitaxially growing aIII-nitride gate layer having a second conductivity type opposite to thefirst conductivity type in the plurality of first recess regions;forming a first dielectric layer on the first hardmask layer and thegate layer, wherein the first dielectric layer comprise a contact regionaligned with each of the plurality of fins and a gate region alignedwith the III-nitride gate layer; forming a photoresist layer on the gateregion of the first dielectric layer; etching the contact region of thefirst dielectric layer using the photoresist layer as a mask to expose aupper surface of the first hardmask layer; removing the photoresistlayer; removing the first hardmask layer to expose a upper surface ofeach of the plurality of III-nitride fins; and epitaxially regrowing aIII-nitride source contact portion coupled to each of the plurality ofIII-nitride fins.

In one embodiment, epitaxial regrowth of the III-nitride source contactportion is a self-limiting process on top of each of the plurality ofIII-nitride fins. In an embodiment, the width of the contact region canbe at least three times the width of each of the plurality ofIII-nitride fins. In a particular embodiment, the III-nitride sourcecontact portion can be characterized by an isosceles triangle shapehaving a base angle in a range between 58 degrees and 65 degrees in across-section view. The III-nitride substrate can be an n-GaN substrate,the first III-nitride layer and the plurality of III-nitride fins caninclude n-GaN epitaxial layers, and the III-nitride gate layer caninclude a p-GaN epitaxial layer. In an embodiment, the III-nitride gatelayer is disposed in the plurality of first recess regions betweenadjacent III-nitride fins of the plurality of III-nitride fins.

In an embodiment, the method also includes forming a first source metallayer overlying the III-nitride source contact portion and the firstdielectric layer, forming a second source metal layer coupled to thefirst source metal layer, forming a third source metal layer coupled tothe second source metal layer, forming a source metal mask layer havingan opening aligned with the gate region of the first dielectric layer,etching the first, second and third source metal layer to expose anupper surface of the gate region of the first dielectric layer, etchingthe gate region of the first dielectric layer to expose a upper surfaceportion of the III-nitride gate layer, and removing the source metalmask layer.

In another aspect of the present invention, a method for forming analignment contact includes: providing a III-nitride substrate;epitaxially growing a first III-nitride layer on the III-nitridesubstrate, wherein the first III-nitride layer is characterized by afirst conductivity type; forming a plurality of III-nitride fins on thefirst III-nitride layer, wherein each the plurality of III-nitride finsis separated by one of a plurality of first recess regions, wherein theplurality of III-nitride fins are characterized by the firstconductivity type; epitaxially regrowing a III-nitride source contactportion on each of the plurality of III-nitride fins; and forming asource contact structure on the III-nitride source contact portions.

In another aspect of the present invention, a method for forming analignment contact includes: providing a III-nitride substrate;epitaxially growing a first III-nitride layer on the III-nitridesubstrate, wherein the first III-nitride layer is characterized by afirst conductivity type; forming a first hardmask layer on the firstIII-nitride layer; forming a plurality of III-nitride fins on the firstIII-nitride layer using the first hardmask layer as a mask, wherein eachof the plurality of III-nitride fins are separated by one of a pluralityof first recess regions, wherein the plurality of III-nitride fins arecharacterized by the first conductivity type; epitaxially growing aIII-nitride gate layer having a second conductivity type opposite to thefirst conductivity type in the plurality of first recess regions;forming a first dielectric layer on the first hardmask layer and theIII-nitride gate layer, wherein the first dielectric layer comprise acontact region aligned with each of the plurality of fins and a gateregion aligned with the III-nitride gate layer; forming a photoresistlayer on the gate region of the first dielectric layer; etching thecontact region of the first dielectric layer using the photoresist layeras a mask to form a second recess region, wherein a upper surface ofeach of the plurality of the III-nitride fins and a portion of uppersurface of the III-nitride gate layer surrounding each of the pluralityof III-nitride fins are exposed from a bottom surface of the secondrecession region; removing the photoresist layer; epitaxially regrowinga III-nitride source contact portion in the second recess region; andremoving the first dielectric layer.

In another aspect of the present invention, a method for forming analignment contact includes: providing a III-nitride substrate;epitaxially growing a first III-nitride layer on the III-nitridesubstrate, wherein the first III-nitride layer is characterized by afirst conductivity type; forming a plurality of III-nitride fins on thefirst III-nitride layer, wherein each of the plurality of III-nitridefins is separated by one of a plurality of first recess regions, whereinthe plurality of III-nitride fins are characterized by the firstconductivity type; epitaxially growing a III-nitride gate layer having asecond conductivity type opposite to the first conductivity type in theplurality of first recess regions; epitaxially growing a secondIII-nitride layer overlying the plurality of the III-nitride fins andthe III-nitride gate layer, wherein the second III-nitride layer ischaracterized by a first dopant concentration; epitaxially growing athird III-nitride layer coupled to the second III-nitride layer, whereinthe third III-nitride layer is characterized by a second dopantconcentration greater than the first dopant concentration; forming afirst source metal layer coupled to the third III-nitride layer; forminga second source metal layer coupled to the first source metal layer;forming a third source metal layer coupled to the second source metallayer; forming a source metal mask layer having an opening aligned witha portion of the III-nitride gate layer; etching the first, second andthird source metal layer to expose a upper surface portion of the thirdIII-nitride layer; etching the third III-nitride layer and the secondIII-nitride layer and a portion of the III-nitride gate layer; andremoving the source metal mask layer.

In one embodiment, the method further includes epitaxially growing aundoped III-nitride cap layer coupled to the III-nitride gate layer.

In one embodiment, etching the third III-nitride layer and the secondIII-nitride layer and the portion of the III-nitride gate layer, mayinclude etching away the undoped III-nitride cap layer in theIII-nitride gate layer. In some embodiments, the III-nitride substratecomprises an n-GaN substrate, the first III-nitride layer comprise ann-GaN epitaxial layer, and the plurality of III-nitride fins comprisen-GaN epitaxial layers.

In another aspect of the present invention, a transistor includes: aIII-nitride substrate; a first III-nitride layer on the III-nitridesubstrate, wherein the first III-nitride layer is characterized by afirst conductivity type; a plurality of III-nitride fins on the firstIII-nitride layer, wherein each of the plurality of III-nitride fins isseparated by one of a plurality of first recess regions, wherein theplurality of III-nitride fins are characterized by the firstconductivity type; a III-nitride gate layer having a second conductivitytype opposite to the first conductivity type in the plurality of firstrecess regions; and a regrown III-nitride source contact portion coupledto each of the plurality of III-nitride fins, wherein the III-nitridesource contact portion is characterized by the first conductivity type.

In one embodiment, the growth of the regrown III-nitride source contactportion is self-limiting on top of each of the plurality of III-nitridefins.

Numerous benefits are achieved by way of the present invention overconventional techniques. For example, embodiments of the presentinvention provide methods and systems that utilize a graded dopingregion as a landing zone for etching of the vertical fin, therebyminimizing the impact of etch depth variation in the etch process on theon-resistance and gate-to-source capacitance of the FET. Moreover, otherembodiments provide a self-aligned source contact to reduce or eliminatealignment issues in the contact formation process and thereby minimizeparasitic capacitances. Additionally, some embodiments utilize anepitaxially-regrown gate layer on the graded doping region including aternary III-V compound on a binary III-V compound substrate.

The difference between the lattice constant of the ternary III-Vcompound gate layer and the binary III-V compound substrate and theinduced strain generates a polarization charge which results in atwo-dimensional electron gas (2DEG) at the interface with the gatelayer. The 2DEG enables a current to first flow substantially in thehorizontal direction along the lateral bottom surface of the gate layer,then in the vertical direction through the drift region, therebyreducing spreading resistance in the device and reducing the devicespecific on resistance. By controlling the etch depth into the gradeddoping region, the drain-source ON resistance, the threshold voltage,the electric field, and the drain-source leakage current can kept withina desired range. Additionally, some embodiments include applications tomerged p-i-n/Schottky (MPS) diodes and to vertical MOSFETs. Inparticular, the use of an epitaxially regrown ternary III-V compound asthe p-type region in an MPS diode can reduce the on-voltage of thediode. The graded doping region landing zone has similar advantages forvertical MOSFETs as for vertical JFETs, and the self-aligned sourcecontact can also be applied to vertical MOSFET structures. These andother embodiments of the invention along with many of its advantages andfeatures are described in more detail in conjunction with the text belowand attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings form a part of the present disclosure, thatdescribe exemplary embodiments of the present invention. The drawingstogether with the specification will explain the principles of theinvention.

FIG. 1 is a cross-sectional view of a vertical-fin-based field effecttransistor (FET) device according to an embodiment of the presentdisclosure.

FIG. 2 is a simplified cross-sectional view of a vertical-fin-based FETdevice illustrating current flow from a lateral direction along atwo-dimensional electron gas (2DEG) to a vertical direction toward thesubstrate according to an embodiment of the present disclosure.

FIG. 3 is a simplified flowchart of a method of fabricating avertical-fin-based FET device according to an embodiment of the presentdisclosure.

FIGS. 4A-41 are cross-sectional views showing intermediate stages of amethod of fabricating a vertical-fin-based FET device according to afirst embodiment of the present disclosure.

FIGS. 4J through 4M are cross-sectional views showing intermediatestages of a method of fabricating a vertical-fin-based FET deviceaccording to a second embodiment of the present disclosure.

FIG. 4N through FIG. 4U are cross-sectional views showing intermediatestages of a method of fabricating a vertical-fin-based FET device thatcan be applied to the first and second embodiments of the presentdisclosure.

FIG. 5 is a simulation structure of a vertical-fin-based FET devicehaving a 0.2 μm fin thickness.

FIG. 6 is a graph illustrating a threshold voltage (in V) of avertical-fin-based FET device as a function of an etch offset (in μm).

FIG. 7 is a graph illustrating an electric field E (in MV/cm) of avertical-fin-based FET device as a function of an etch offset (in μm).

FIG. 8 is a graph illustrating channel leakage (in A) of avertical-fin-based FET device as a function of an etch offset (in μm).

FIG. 9A is a graph illustrating a current density for a normal etch.

FIG. 9B is a graph illustrating a current density for a 0.1 μm overetch.

FIG. 9C is a graph illustrating a current density for a 0.2 μm overetch.

FIG. 10A is a graph illustrating an electric field at the gate cornerfor a normal etch.

FIG. 10B is a graph illustrating an electric field at the gate cornerfor a 0.1 μm underetch.

FIG. 10C is a graph illustrating a current density for a 0.2 μmunderetch.

FIG. 11 is a graph illustrating the on-resistance Ron as a function ofetch variation (μm) for the 0.2 μm graded epitaxial layer.

FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a functionof etch variation (μm) for the 0.2 μm graded epitaxial layer.

FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as afunction of etch variation (μm) for the 0.2 μm graded epitaxial layer.

FIG. 14 is a graph illustrating a high-voltage drain leakage currentIdss (A) at 1200V as a function of etch variation (μm) for the 0.2 μmgraded epitaxial layer.

FIG. 15 is a graph illustrating the on-resistance Ron (mΩ) as a functionof etch variation (μm) for the 0.3 μm graded epitaxial layer.

FIG. 16 is a graph illustrating a threshold voltage Vt (V) as a functionof etch variation (μm) for the 0.3 μm graded epitaxial layer.

FIG. 17 is a graph illustrating an electric field (MV/cm) as a functionof etch variation (μm) for the 0.3 μm graded epitaxial layer.

FIG. 18 is a graph illustrating a high-voltage drain leakage currentIdss (A) at 1200V as a function of etch variation (μm) for the 0.3 μmgraded epitaxial layer.

FIG. 19A is a graph illustrating an effect of no polarization charge onthe current density predicted to result at the c-planeIn_(0.15)Ga_(0.85)N/GaN interface.

FIG. 19B is a graph illustrating an effect of the polarization chargepredicted to result at the c-plane In_(0.15)Ga_(0.85)N/GaN interfaceaccording to some embodiments of the present disclosure.

FIG. 20A is a graph illustrating an effect of an electric fieldpredicted to result at the interface between the c-planeIn_(0.15)Ga_(0.85)N gate layer and the GaN drift layer.

FIG. 20B is a graph illustrating an effect of an electric fieldpredicted to result at the c-plane In_(0.15)Ga_(0.85)N/GaN interfaceaccording to some embodiments of the present disclosure. The graph showsa relatively high electric field is formed due to the polarization in anoff state.

FIG. 20C is a graph illustrating the off-state magnitude of electricfield without polarization and with polarization.

FIG. 21A is a graph illustrating current density through the channel ofa baseline FET.

FIG. 21B is a graph illustrating current density through the channel ofa non-polar FET.

FIG. 21C is a graph of current density through the channel of thebaseline FET compared with that of the non-polar FET.

FIG. 21D is a graph of the band diagrams of the baseline FET comparedwith that of the non-polar FET.

FIG. 22A through FIG. 22J are cross-sectional views showing intermediatestages of a method of fabricating a vertical-fin-based FET deviceaccording to an embodiment of the present disclosure.

FIG. 23A through FIG. 23G are cross-sectional views showing intermediatestages of a method of fabricating a vertical-fin-based FET deviceaccording to an embodiment of the present disclosure.

FIG. 24A through FIG. 24G are cross-sectional views showing intermediatestages of a method of fabricating a vertical-fin-based FET deviceaccording to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

Embodiments of the present disclosure will be described more fullyhereinafter with reference to the accompanying drawings. The disclosuremay, however, be embodied in many different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of the invention to thoseskilled in the art. The features may not be drawn to scale, some detailsmay be exaggerated relative to other elements for clarity. Like numbersrefer to like elements throughout.

Embodiments of the present disclosure relate to vertical-fin-based fieldeffect transistor (FET) devices. More particular, the present disclosurerelates to vertical fin-based FET devices with improved leakage current,maximum electric field, and on-resistance for a given threshold voltage.Merely by way of example, the present disclosure relates to methods andvertical transistor devices with a graded doping zone in the doped driftregion, and a regrown epitaxial gate layer in direct contact with thegraded doping zone. Many advantages can be obtained by having theepitaxially regrown gate layer on the graded doping zone, such asimproved on-resistance, maximum electric field, and current flow firstin the lateral direction along the bottom interface layer of the gatelayer than in the vertical direction through the drift layer toward thesubstrate.

FIG. 1 is a cross-sectional view of a vertical fin-based field effecttransistor device 100 according to an embodiment of the presentdisclosure. The terms “FET,” “FinFET,” and “vertical fin-based FET” areused interchangeable herein. Referring to FIG. 1 , FET device 100 mayinclude a semiconductor substrate 101, a drift layer 102 including auniformly doped region 102 a on semiconductor substrate 101 and a gradeddoping region 102 b on uniformly doped region 102 a, and a plurality offins 103 protruding from graded doping region 102 b. In one embodiment,each of the fins 103 may include a heavily doped layer 104 disposed inan upper portion of the fin and a metal layer 105 including materialsincluding a refractory metal, refractory metal compound or refractorymetal alloy layer (e.g., a TiN layer) disposed on heavily doped layer104. FET device 100 may also include a source contact structure 106 onmetal layer 105 (e.g., TiN). Source contact structure 106 may include atitanium (Ti) layer 106 a on metal layer 105 (e.g., TiN), an aluminum(Al) layer 106 b on titanium (Ti) layer 106 a, and a barrier metal layer(e.g., molybdenum (Mo), titanium (Ti), tantalum (Ta), or similar) 106 con aluminum (Al) layer 106 b.

FET device 100 may further include a gate layer 110 having a bottomportion in direct contact with graded doping region 102 b, an insulatinglayer 111, for example, a dielectric (e.g., silicon dioxide or siliconnitride) layer disposed on gate layer 110 and surrounding fins 103, agate contact structure 112 disposed on gate layer 110, a firstinterlayer dielectric layer 113 disposed on insulating layer 111 andgate contact structure 112, and a second interlayer dielectric layer 114disposed on first interlayer dielectric layer 113. In one embodiment,gate contact structure 112 may include a nickel (Ni) layer 112 adisposed on gate layer 110, a first gold (Au) layer 112 b disposed onnickel (Ni) layer 112 a, a barrier metal (e.g., molybdenum (Mo),titanium (Ti), tantalum (Ta), or similar) layer 112 c disposed on firstgold (Au) layer 112 b, and a second gold (Au) layer 112 d disposed onbarrier layer 112 c.

FET device 100 may also include a first via contact 115 extendingthrough first and second interlayer dielectric layers 113, 114 and incontact with source contact structure 106, a second via contact 116extending through first and second interlayer dielectric layers 113, 114and in contact with gate contact structure 112, and a drain metalcontact 117 on the bottom surface of semiconductor substrate 101. Asused herein, the terms “drift layer” and “drift region” are usedinterchangeably, the terms “doped layer” and “doped region” are usedinterchangeably, and the terms “graded doping region” and “graded dopinglayer” are used interchangeably.

In some embodiments, semiconductor substrate 101 may include an N+ dopedIII-nitride material, fins 103 may include an N doped III-nitridematerial having a first dopant concentration, uniformly doped region 102a of drift layer 102 may include an N doped III-nitride material havinga second dopant concentration lower than the first dopant concentration,and graded doping region 102 b having a third dopant concentration thatlinearly increases from the second dopant concentration to the firstdopant concentration.

In one embodiment, the first dopant concentration is about 7.5×10¹⁶atoms/cm 3 and the second dopant concentration is about 1×10¹⁶ atoms/cm3.

In one embodiment, the drift region has a thickness of about 12 μm, thegraded doping region has a thickness of about 0.3 μm, and thesemiconductor fin has a height in a range between about 0.7 μm and 0.8μm and a width of about 0.2 μm.

In one embodiment, gate layer 110 may include an In_(x)Ga_(1-x)N layer,where 0<x<1, i.e., x is between 0 and 1 and is not equal to 0 or 1. Inone embodiment, gate layer 110 is disposed in a recess region betweentwo adjacent fins and has a portion 110 a in contact with graded dopingregion 102 b. The depth (or the thickness) of portion 110 a of the gatelayer may affect the threshold voltage, the conductance, the maximumelectric field of the FET device. The effect of the depth (or thickness)of portion 110 a embedded in the graded doping region will be describedin more detail below.

In one embodiment, the FET device 100 may include a semiconductorsubstrate 101 that may include an N+ GaN material layer, a drain metalcontact 117 disposed at its bottom surface, an N GaN drift layer 102having a uniformly doped region 102 a disposed on semiconductorsubstrate 101 and a graded doping region 102 b disposed on the uniformlydoped region 102 a, and an epitaxial GaN layer disposed on the gradeddoping region and including a recess region for forming a plurality offins 103. The FET device may also include a gate layer 110, for example,a p-type GaN gate layer, filling the recess region. The graded dopingregion 102 b may function as a landing pad to ensure sufficient contactfor gate layer 110. In one embodiment, the gate layer may include aternary compound semiconductor layer (e.g., an In_(x)Ga_(1-x)N layer,where 0<x<1). In one embodiment, portion 110 a of the gate layer 110 mayhave a depth (or thickness) of about 0.1 μm (+/−0.1 μm) extending intograded doping region 102 b. The fins each may have a width of about 0.2μm and are spaced from each other by a space of about 2.0 μm, i.e., therecess region or the gate layer filling the recess region between twoadjacent fins has a lateral width of about 2.0 μm. The FET device mayalso include a two-dimensional electron gas (2DEG) layer 120 formed inan interface between gate layer 110 and graded doping region 102 b. Thesurface area of gate layer 110 is large, so that a current flowslaterally along 2DEG layer 120 before flowing vertically toward drainmetal layer 117 in the direction of the substrate, thereby improving theconductance (reducing the on-resistance) of the FET device. In otherwords, the channel FET device has two portions, with a first portionbeing a lateral channel that controls the current flow through the 2DEGlayer, which distributes the current efficiently in the drift region,and a second portion being a vertical channel which carries the currentvertically through the drift region toward semiconductor substrate 101and drain metal layer 117.

In one embodiment, each of the fins may include a metal layer 105 madeof TiN and a multilayer source metal structure (e.g., stacked layers ofTi/Al or Ti/TiN/Al in which Ti is in contact with metal layer 105. TheFET device may also include an insulating layer 111, e.g., a silicondioxide or silicon nitride layer on gate layer 110. Insulating layer 111includes an opening where a gate contact structure 112 (i.e., a gateelectrode) is formed in contact with gate layer 110. Gate contactstructure 112 (i.e., a gate electrode) has a multilayer structure ofmetals, e.g., Pd/Pt/Au, where Pd is in contact with gate layer 110, orNi and Au, in which the Ni is deposited in contact with gate layer 110.Other embodiments can include other gate electrode metal structuresknown to those skilled in the art.

In one embodiment, each of the fins may include an upper portion havingsidewalls parallel to each other and substantially perpendicular to thesurface of the substrate and a lower portion having sidewallsnon-parallel to each other and forming an angle other than 90 degreeswith the surface of the substrate. The parallel sidewalls may define anon-polar plane, such as an m-plane.

In one embodiment, the 2DEG layer is induced by a polarization betweenthe gate layer and the drift region in a c-plane, and the currentflowing vertically through the drift region is along an m-plane.

FIG. 2 is a simplified cross-sectional view of a vertical FET device 200illustrating a current flow from a lateral direction along a 2DEG to avertical direction toward the substrate according to an embodiment ofthe present disclosure. Referring to FIG. 2 , vertical FET device 200may include a substrate 201, a drift layer 202 overlying substrate 201,a plurality of fins 203 protruding from a surface of drift layer 202, agate layer 210 on drift layer 202 and surrounding the fins. FET device20 may further include a gate electrode 212 on gate layer 210, and adielectric layer (e.g., silicon dioxide) 211 on gate layer 210 andsurrounding fins 203 and gate electrode 212. FET device 20 may alsoinclude a two-dimensional electron gas 220 where gate layer 220 meetsdrift layer 202 along the polar plane directions. FET device 20 may alsoinclude a source electrode 206 coupled to fins 203. FET device 20 is inan off-state when no electrical potential is applied to gate electrode212.

When an electrical potential is applied to gate electrode 212, itmodulates a continuous two-dimensional electron gas (2DEG) 220 that iselectrically communicative with the drain electrode. The source current231 flows laterally under gate layer 210 and vertically into drainelectrode 217. In one embodiment, the fins each have a width of about0.2 μm and are spaced apart by a distance of about 2.0 μm. Apolarization-induced 2DEG 220 is formed in the interface between thegate layer and the graded doping region of the drift region, therebydistributing the current in the drift region to improve the conductanceof the FET device.

Embodiments of the present disclosure further provide a method offabricating a vertical FET device. FIG. 3 is a simplified flowchart of amethod 300 of fabricating a vertical FET device with a regrown gatelayer according to an embodiment of the present disclosure. Referring toFIG. 3 , a III-nitride substrate is provided (310). In an embodiment,the III-nitride substrate is an N+ GaN substrate having a resistivity ina range of about 0.020 ohm-cm. In one embodiment, the resistivity of theN+ GaN substrate may be from about 0.001 ohm-cm to 0.018 ohm-cm,preferably less than 0.016 ohm-cm, and more preferably, less than 0.012ohm-cm. Method 300 also includes forming a first III-nitride epitaxiallayer, for example, a 12 μm thick first III-nitride epitaxial layer(e.g., an N− GaN epitaxial layer) deposited on the III-nitride substrate(312). The first III-nitride epitaxial layer is epitaxially grown on theIII-nitride substrate at a temperature between 950° C. and 1100° C. andis characterized by a first dopant concentration, e.g., N-type dopingwith a dopant concentration of about 1×10¹⁶ atoms/cm³. In someembodiments, the first III-nitride epitaxial layer is a drift layerincluding a uniformly doped region (layer) on the III-nitride substrateand a graded doping region (layer) on the uniformly doped region. In anembodiment, the uniformly doped region has a thickness of about 12 μm,and the graded doping region has a thickness of about 0.3 micron. In anembodiment, the surface of substrate 310 is miscut from the c-plane atan angle to facilitate high-quality epitaxial growth for high-voltageoperation of the drift layer.

Method 300 further includes forming a second III-nitride epitaxial layeron the first III-nitride epitaxial layer (314). In an embodiment, thesecond III-nitride epitaxial layer is epitaxially grown on the firstIII-nitride epitaxial layer with a thickness of about 0.7 μm and ischaracterized by a second dopant concentration, e.g., N-type doping. Thesecond dopant concentration is higher than the first dopantconcentration in some embodiments. In an embodiment, the second dopantconcentration is about 1.3×10¹⁷ atoms/cm³. Method 300 further includesforming a metal layer on the second III-nitride epitaxial layer and apatterned hardmask layer on the metal layer, and patterning the metallayer using the patterned hardmask layer as a mask (316). Method 300further includes forming a recess region in the second III-nitrideepitaxial layer using the patterned hardmask layer by an etch process,e.g., a reactive ion etching (RIE) process (318). Method 300 furtherincludes regrowing a third III-nitride epitaxial layer in the recessregion (320). The regrown III-nitride epitaxial layer may form a gatelayer. In one embodiment, the regrown III-nitride epitaxial layer has aconductivity type opposite the conductivity type of the first and secondIII-nitride epitaxial layers.

Method 300 further includes forming a first dielectric layer on theregrown III-nitride epitaxial layer and on the patterned hardmask layerand a second dielectric layer on the first dielectric layer (322).Method 300 further includes removing a portion of the second dielectriclayer to form a spacer on sidewalls of the first dielectric layer onopposite sides of an upper portion of the fins (324). Method 300 furtherincludes removing a portion of the first dielectric layer to expose asurface portion of the regrown III-nitride epitaxial layer while leavinga portion of the first dielectric layer on opposite sides of the fins(326). Method 300 further includes removing the spacer and the hardmasklayer while exposing a surface of the metal layer and keeping theportion of the first dielectric layer on opposite sides of the fins(328).

Method 300 further includes forming a source mask layer on the exposedsurface portion of the regrown epitaxial III-nitride layer (330). Method300 further includes forming a source contact structure on the surfaceof the metal layer and removing the source mask layer (332). Method 300further includes forming a gate mask layer covering the source contactstructure while exposing a surface portion of the regrown III-nitrideepitaxial layer, forming a gate contact structure on the exposed surfaceportion of the regrown III-nitride epitaxial layer, and removing thegate mask layer (334). Method 300 further includes forming an interlayerdielectric layer covering the source contact structure and the gatecontact structure, forming a patterned mask layer on an interlayerdielectric layer, etching the interlayer dielectric layer to formthrough holes extending to the source contact structure, and filling thethrough holes with a conductive material to form vias (336). It is notedthat the through holes and vias to the gate contact structure can beformed concurrently with the formation of the through holes and vias tothe source contact structure.

It should be appreciated that the specific steps illustrated in FIG. 3provide a particular method of fabricating a vertical FET device with aregrown gate layer according to an embodiment of the present invention.Other sequences of steps may also be performed according to alternativeembodiments. For example, alternative embodiments of the presentinvention may perform the steps outlined above in a different order.Moreover, the individual steps illustrated in FIG. 3 may includemultiple sub-steps that may be performed in various sequences asappropriate to the individual step. Furthermore, additional steps may beadded or removed depending on the particular application. One ofordinary skill in the art would recognize many variations,modifications, and alternatives.

Referring once again to FIG. 3 and with reference to FIGS. 4A through4U, cross-sectional views showing intermediate stages of various methodsof fabricating a vertical-fin-based FET device are shown according toseveral embodiments of the present disclosure. Referring to FIG. 4A, anN+ doped III-nitride substrate 401 is provided (block 310). A firstN-doped semiconductor (drift) layer, referred to as first semiconductorlayer 402, is epitaxially grown on N+ doped III-nitride substrate 401(block 312) at a temperature between 950° C. and 1200° C., preferablybetween 1000° C. and 1150° C., and more preferably about 1100° C. InFIG. 4B, a graded doping region 460 having a thickness of about 0.3 μmis disposed between the first and second semiconductor layers and has adopant concentration that linearly increases from about 1×10¹⁶ atoms/cm³to 1.3×10¹⁷ atoms/cm³, i.e., from the first semiconductor layer towardthe second semiconductor layer.

A second N doped semiconductor layer 403 is epitaxially grown on firstsemiconductor layer 402 (block 314) at a temperature between 950° C. and1200° C., preferably between 1000° C. and 1150° C., and more preferablyabout 1100° C. Referring to FIG. 4B, a metal layer 405 is formed onsecond semiconductor layer 403, and a patterned hardmask layer 406 isformed on metal layer 405 (block 316). In one embodiment, a heavily N+doped layer 404 may be present between second semiconductor layer 403and metal layer 405 to improve contact resistance between the secondsemiconductor layer and the metal layer. In an embodiment, a hardmasklayer may include Si₃N₄ and is formed with a thickness of about 400 nmby PECVD at about 300° C. In an embodiment, patterned hardmask layer 406may be formed using RIE with F-based chemistry. In an embodiment, metallayer 405 is omitted.

In an embodiment, N+ doped III-nitride substrate 401 is heavily dopedwith N-type dopants in a dopant concentration in a range of about 5×10¹⁷atoms/cm³ to about 1×10¹⁹ atoms/cm³ and a resistivity of less than 0.020ohm-cm. In one embodiment, the resistivity of the N+ doped III-nitridesubstrate may be from about 0.001 ohm-cm to 0.018 ohm-cm, preferablyless than 0.016 ohm-cm, and more preferably, less than 0.012 ohm-cm.First semiconductor layer 402 is a drift layer having a thickness ofabout 12 μm in a dopant concentration in a range of about 1×10¹⁶atoms/cm³. Second semiconductor layer 403 is a fin conduction layerhaving a uniform doped region with N-type dopants of about 1.3×10¹⁷atoms/cm³ and a thickness of about 12 μm. Metal layer 405 may includeTiN, and hardmask layer 406 may include silicon nitride. In some of thefollowing drawings and figures, graded doping region 460 and heavily N+doped layer 404 are omitted for the sake of clarity.

Referring to FIG. 4C, an etch process is performed using the patternedhardmask 406 as a mask to form a plurality of fins 403′ (block 318). Insome embodiments, the fins each have a width of about 0.2 μm, a heightin a range between about 0.7 μm and 0.8 μm, and are spaced apart fromeach other by a space of about 2 μm, i.e., the fin pitch is about 2 μm.To achieve uniform height of the fins, good controllability of the depthof the etch process is required. In accordance with the presentdisclosure, an etch process may include Cl-based chemistry using RIE andis carried out to remove a portion of second semiconductor layer 403 toform a recess region 408. In an embodiment, the etch process may stopwhen about 0.1 μm of graded doping region 460 is removed. The use of thegraded doping region to mitigate the electrical effects of the etchprocess variation or tolerance is utilized as will be described indetail further below.

It is noted that the bottom portion of the fins may have a shapedifferent from the shape shown in FIG. 4C after the etch process.Embodiments of the present disclosure are described herein withreference to cross-section illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofthe invention. The thickness of layers and regions in the drawings maybe exaggerated for clarity. Additionally, variations from the shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. In the following drawings, thebottom portion of the fins are shown as having a 90 degrees angle withthe surface of the graded doping region, i.e., the fins are shown ashaving a cross-sectional rectangular shape. It is understood that thebottom portion of the fins may have rounded or curved features. Thus,the regions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of the invention.

In one embodiment, after forming the trench, a cleaning process iscarried using a TMAH solution of about 25% by weight, at a temperatureof about 85° C., and for a duration of about 30 minutes. In anotherembodiment, prior to performing a cleaning using the TMAH solution, apre-cleaning such as piranha clean using a H₂SO₄:H₂O in a volume ratio2:1 for 2 minutes may also be performed.

Referring to FIG. 4D, after the cleaning, a third semiconductor layer407 is epitaxially grown in recess region 408 (block 320). In anembodiment, third semiconductor layer 407 may include a p-type GaN layerthat is grown non-conformally in the trench at a temperature of about950° C. up to a thickness that is substantially planar to the bottom ofmetal layer 405′ (or hardmask 406′, if metal layer 405′ is omitted). Inone embodiment, the thickness of third semiconductor layer 407 is about840 nm. The p-type GaN layer may be doped with Mg with a dopantconcentration of about 1×10¹⁹ atoms/cm³. The p-type GaN layer may bedoped with Mg with a dopant concentration of about 1×10¹⁹ atoms/cm³.Thereafter, a thermal anneal (e.g., a rapid thermal annealing in N₂ at850° C. for 5 minutes) is performed to activate the Mg dopant atoms. TheMg atoms are then activated in the p-type GaN layer in an amount ofgreater than 10% by weight. In one embodiment, a remaining portion of aheavily N+ doped layer 404 (as shown in FIG. 4B) may be present betweenfins 403′ and metal layer 405′ to improve contact resistance between thefins 403′ and the metal layer 405′.

In a first embodiment, referring to FIG. 4E, a planarization process maybe performed on third semiconductor layer 407. In an embodiment, theplanarization process includes removing an upper portion of thirdsemiconductor layer 407 by etching. In an embodiment, the planarizationprocess includes removing about 0.2 μm of the upper portion of thirdsemiconductor layer 407.

Thereafter, a first dielectric layer 410 a is formed on at least theplanarized surface of fourth dielectric semiconductor layer 407, andsubstantially conformal to the sidewall of the fin, the metal layer 405′and the hardmask 406′. In an embodiment, the first dielectric layer 410a has a thickness of approximately 100 nm and may include Si₃N₄ and bedeposited by PECVD at about 300° C. A second dielectric layer 410 b isformed on first dielectric layer 410 a. In an embodiment, seconddielectric layer 410 b has a thickness of approximately 100 nm and mayinclude SiO₂ and be deposited by PECVD at about 300° C. A thirddielectric layer 410 c is formed on second dielectric layer 410 b. In anembodiment, third dielectric layer 410 c has a thickness ofapproximately 400 nm and may include Si₃N₄ and be deposited by PECVD atabout 300° C.

Referring to FIG. 4F, third dielectric layer 410 c (shown in FIG. 4E) isetched back to form a spacer 412 a on the sidewalls of second dielectriclayer 410 b. In one embodiment, spacer 412 a has a width at the foot ofabout 300 nm.

Referring to FIG. 4G, second dielectric layer 410 b is etched using asubstantially isotropic etch to expose the top of first dielectric layer410 a over planarized region 407 and over hardmask 406′. In oneembodiment, the etch uses a wet etchant such as buffered HF; in anotherembodiment the etch uses a F-based plasma etch. After etching, theremaining portion of second dielectric layer 410 b adjacent to spacer412 a is denoted 410 b′.

Referring to FIG. 4H, third dielectric layer 410 c (spacer 412 a), firstdielectric layer 410 a, and hardmask 406′ are etched to expose thecontact region over metal layer 405′. In one embodiment, metal layer405′ is omitted, and the contact region is the top of fin 403′.

Referring to FIG. 4I, the remaining portion of second dielectric layer410 b′ (shown in FIG. 4H) is etched to expose the remaining surface offirst dielectric layer 410 a.

FIG. 4J through FIG. 4M are cross-sectional views showing intermediatestages of a method of fabricating a vertical-fin-based FET deviceaccording to a second embodiment of the present disclosure. In thesecond embodiment, starting with the structure shown in FIG. 4D, andreferring to FIG. 4J, a planarization process may be performed on thirdsemiconductor layer 407. In an embodiment, the planarization processincludes removing an upper portion of third semiconductor layer 407 byetching. In an embodiment, the planarization process includes removingabout 0.2 μm of the upper portion of third semiconductor layer 407.Thereafter, a first dielectric layer 450 is formed on the planarizedsurface of fourth semiconductor layer 407, and a second dielectric layer452 is formed on first dielectric layer 450. In an embodiment, firstdielectric layer 450 may include SiO₂ and be deposited by PECVD at about300° C. Second dielectric layer 452 may include Si₃N₄ and be depositedby PECVD at about 300° C.

Referring to FIG. 4K, second dielectric layer 452 is etched back to forma spacer 454 having a thickness of about 2,000 Å on sidewalls of firstdielectric layer 450. In one embodiment, first dielectric layer 450 isalso etched back by a certain depth such that the upper surface of firstdielectric layer 450 is within the thickness of hardmask layer 406′, asshown in FIG. 4K.

Referring to FIG. 4L, first dielectric layer 450 is further etched backexposing an upper surface of fourth semiconductor layer 407. In anembodiment, first dielectric layer 450 may be over-etched by an amountof 50% to expose an upper surface and a portion of sidewalls of hardmasklayer 406′.

Referring to FIG. 4M, hardmask layer 406′ and spacer 454 are removedwhile retaining the remaining portion of first dielectric layer 450. Forpurposes of clarity, metal layer 405′ has been removed, but it can beutilized to make electrical contact to fins 403′ and be included in thedevice structure as will be evident to one of skill in the art.

FIG. 4N through FIG. 4U are cross-sectional views showing intermediatestages of a method of fabricating a vertical fin-based FET that can beapplied to the first and the second embodiments. For purposes ofillustration, FIG. 4N through 4U are applied to the second embodimentand those skilled in the art can readily apply the same intermediatestages to the first embodiment. Referring to FIG. 4N, a source masklayer 415 is formed overlying the exposed upper surface of fourthsemiconductor layer 407 and having an opening 415 a exposing a portionof first dielectric layer 450 and an upper surface of fins 403′. Sourcemask layer 415 also has an overhang 415 b extend over opening 415 a. Inan embodiment, source mask layer 415 is lift-off capable and has abottom CD of 0.65 μm and a top CD of 0.55 μm.

Referring to FIG. 4O, a source metal contact structure 416 is formed bydeposition at a temperature of about 150° C. on the exposed uppersurface of fins 403′. In an embodiment, source metal contact structure416 may include a stack structure comprising a first source metal layer416 a on the upper surface of fins 403′, a second source metal layer 416b on first source metal layer 416 a, and a third source metal layer 416c on second source metal layer 416 b. If metal layer 405′ is present,first source metal layer 416 a is on the first metal layer 405′. In anembodiment, first source metal layer 416 a includes Ti having athickness of about 25 nm, second source metal layer 416 b includes Alhaving a thickness of about 100 nm, and third source metal layer 416 cincludes Mo having a thickness of about 40 nm. In another embodiment,second source metal layer 416 b includes TiN and third source metal 416c includes Al. In another embodiment, second source metal layer 416 bincludes TiN and third source metal 416 c is omitted. After forming thesource metal contact structure, source mask layer 415 is dissolved tolift off the metal layers deposited thereon, while the metal layersdeposited on the upper surface of the fins remain intact. In anotherembodiment, source mask layer 415 is applied in reverse tone afterdeposition of source metal contact structure 416, and source metalcontact structure 416 is etched (e.g., using RIE) except wherereverse-tone mask layer 415 is present. Source mask layer 415 is thenremoved. Source metal contact structure 416 formed below opening 415 awill have a width of approximately 0.65 μm corresponding to the width ofthe opening. In an embodiment, a rapid temperature annealing (RTA)treatment may be performed in N₂ at 850° C. for 5 minutes. After the RTAtreatment, the source metal contact structure will have a specificresistance of less than about 10⁻⁵ ohm-cm.

In some embodiments, a junction-terminated edge (JTE) structure isformed outside the FET device active area by implantation (e.g.,implanting nitrogen (N) or argon (Ar)) to enable stable high-voltageoperation of the device.

Referring to FIG. 4P, a gate metal mask layer 420 is formed overlyingthe exposed upper surface of the source metal structure and having anopening 420 a exposing a surface portion of fourth semiconductor layer407. Gate metal mask layer 420 also has an overhang 420 b extending overopening 420 a. In an embodiment, gate metal mask layer 420 is lift-offcapable and has a bottom CD of 0.9 μm and a top CD of 0.8 μm.

Referring to FIG. 4Q, a gate metal contact structure 421 is formed bydeposition through opening 420 a onto the exposed surface portion offourth semiconductor layer 407. In an embodiment, gate metal contactstructure 421 may include a stack structure comprising a first gatemetal layer 421 a on the surface portion of fourth semiconductor layer407, a second gate metal layer 421 b on first gate metal layer 421 a, athird gate metal layer 421 c on second gate metal layer 421 b, and afourth gate metal layer 421 d on third gate metal layer 421 c. In anembodiment, first gate metal layer 421 a includes Ni, second gate metallayer 421 b includes Au, third gate metal layer 421 c includes Mo, andfourth gate metal layer 421 d includes Au. In another embodiment, gatemetal layers 421 c and 421 d are omitted, and first gate metal layer 421a includes Ni and second gate metal 421 b includes Au. In anotherembodiment, gate metal layer 421 d is omitted, and first gate metallayer 421 a includes Pd, second gate metal 421 b includes Pt, and thirdgate metal layer 421 c includes Au. After forming the gate metal contactstructure, gate metal mask layer 420 is dissolved to lift off the metallayers deposited on the gate mask layer while the metal layers depositedon the surface portion of fourth semiconductor layer 407 remain intact.

Referring to FIG. 4R, gate metal mask layer 420 is removed and a thermalanneal is performed to provide a stable, low contact resistance contact.In an embodiment, a rapid thermal annealing (RTA) treatment may beperformed in O₂ at 500° C. for 10 minutes. After the thermal treatment,the gate metal contact structure 421 will have a specific resistance ofless than about 10⁻³ ohm-cm.

Referring to FIG. 4S, a first interlayer dielectric layer 425 isdeposited covering the gate metal contact structure 421, the sourcemetal contact structure 416, and the surface of the fourth semiconductorlayer 407, using a plasma enhanced chemical vapor deposition (PECVD)process at a temperature of 300° C. First interlayer dielectric layer425 is relatively conformal. In an embodiment, first interlayerdielectric layer 425 has a thickness of approximately 50 nm and mayinclude nitride (e.g., silicon nitride). Next, a second interlayerdielectric layer 426 is deposited on first interlayer dielectric layer425 using a plasma enhanced chemical vapor deposition (PECVD) process ata temperature of 300° C. (block 336). Second interlayer dielectric layer426 has a thickness of approximately 50 nm and may include oxide (e.g.,silicon oxide).

Referring to FIG. 4T, a patterned photoresist layer 427 is formed oversecond interlayer dielectric layer 426, which can be planarized orun-planarized. Patterned photoresist layer 427 is formed and patternedwith well-known photolithography processes to define locations where avia hole 428 is to be formed. Next, first and second interlayerdielectric layers 425, 426 are etched until an upper surface of thesource metal contact structure 416 is exposed. In some embodiments, avia hole to the gate metal contact structure 421 may also be formedconcurrently with via hole 428 for the source metal contact structure.In an embodiment, the via hole has a CD of approximately 0.45 μm.

Next, patterned photoresist layer 427 is removed. Referring to FIG. 4U,a conductive material 429 is formed filling via hole 428, and a padmetal deposition is performed on the filled via hole by evaporation to athickness of about 4 μm. The above described method of fabricating avertical fin-based FET is advantageous in that a metal, metal alloy, ormetal compound layer (e.g., TiN) is formed on the fin epitaxial layerfollowed by a hardmask layer.

FIG. 5 is a cross-sectional view of a simulation cell structure using a0.2 μm fin width. The nominal etch depth is 0.1 μm below the bottom ofthe fin layer (0.1 μm into the graded zone). Etch depth variations of+/−0.1 μm around the nominal were simulated, as well as a graded zonethickness of 0.2 μm for the second round and 0.3 μm for the third roundof simulations.

FIG. 6 is a graph illustrating a threshold voltage (in V) of a verticalfin-based FET device as a function of an etch offset (in μm) for a 0.3μm fin and an ungraded epitaxial layer. The “0” on the x-axis representsthe interface between the fin and the drift region. Positive values forthe etch offset indicate an overetch into the drift region below the finlayer, and negative values for the etch offset indicate an underetch.The y-axis represents the voltage threshold (V). Referring to FIG. 6 ,an overetch into the drift region below the fin layer results in adramatic increase in the voltage threshold. Thus, the inventors havediscovered the acceptable limit with respect to an overetch into thedrift region for the conductance and the threshold voltage is about 0.1μm.

FIG. 7 is a graph illustrating an electric field E (in MV/cm) of avertical fin-based FET device as a function of an etch offset (in μm)for a 0.3 μm fin and an ungraded epitaxial layer. The “0” on the x-axisrepresents the interface between the fin and the drift region. Positivevalues for the etch offset indicate an overetch into the drift regionbelow the fin layer, and negative values for the etch offset indicate anunderetch. The y-axis represents the electric field E (MV/cm). Anunderetch of the epitaxial layer (i.e., above the interface with thedrift layer) results in a significant increase of the maximum E field.That is, the breakdown risk increases with an underetch of 0.1 μm ormore.

FIG. 8 is a graph illustrating channel leakage (in A) of a verticalfin-based FET device as a function of an etch offset (in μm) for a 0.3μm fin and an ungraded epitaxial layer. The “0” in the x-axis representsthe interface between the fin and the drift region. Positive values forthe etch offset indicate an overetch into the drift region below the finlayer, and negative values for the etch offset indicate an underetch.The y-axis represents the drain-source leakage current Idss (A).Referring to FIG. 8 , there is no significant impact of the etchvariation on the leakage current.

FIG. 9A is a graph illustrating a current density for a normal etch.FIG. 9B is a graph illustrating a current density for a 0.1 μm overetch.FIG. 9C is a graph illustrating a current density for a 0.2 μm overetch.Thus, these graphs illustrate current density (A/cm 2) as a function ofposition relative to the fin for several etch conditions for a 0.3 μmfin and an ungraded epitaxial layer. The fin is located at the rightside of each graph. The solid horizontal line 910 is the nominal etchdepth, and the dashed line 901 shows the fin/drift region interface. Thex-axis represents the position of the current density in micronsrelative to the fin, where “1” corresponds to the middle of the fin. They-axis represents the position of the etched drift region relative tothe gate layer, where “0” corresponds to the upper surface of the gatelayer, and “0.8” corresponds to the nominal bottom position of the gatelayer.

Referring to FIG. 9A, for a nominal etch that terminates at the bottomof the gate layer, i.e., the etch depth is 0.8 μm and terminates at theinterface with the drift region, the high current density is around theinterface between the bottom of the gate layer and the bottom of thefin, and the threshold voltage is in a nominal range. In FIG. 9B, whichillustrates a current density for a 0.1 μm overetch, the interface withthe bottom of the gate layer is located at 0.9 μm. The threshold voltageis high as indicated by the strip 902. In FIG. 9C, which illustrates acurrent density for a 0.2 μm overetch, the threshold voltage is worse asindicted by the strip 903. The results are also confirmed in FIG. 6 ,which shows a significant increase in the threshold voltage at 0.2 μmoveretch.

FIG. 10A is a graph illustrating an electric field at the gate cornerfor a normal etch. FIG. 10B is a graph illustrating an electric field atthe gate corner for a 0.1 μm underetch. FIG. 10C is a graph illustratinga current density for a 0.2 μm underetch. As illustrated, these graphsshow the electric field at the gate corner for different etchconditions. The nominal etch condition is indicated by the horizontalline 1010 marked as “N/N− Interface.” FIG. 10A is a graph illustratingthe electric field 1001 having a nominal value at the gate corner for anormal etch. The double arrow 1002 shows the heavily doped region belowthe interface with the gate layer. FIG. 10B is a graph illustrating anelectric field 1003 at the gate corner for a 0.1 μm underetch. Thedouble arrow 1004 shows a portion of the heavily doped region disposedbetween the gate layer and the underetched region, which may cause ahigh electric filed at the gate corner. FIG. 10C is a graph illustratingan electric field for a 0.2 μm underetch. The high-field region(indicated by ellipse 1007 in FIG. 10B and ellipse 1008 in FIG. 10C) arenear the gate corner with the fin. The heavily doped region, indicatedby the double arrow 1006, is entirely disposed in the underetchedregion.

0.2 μm Fin with 0.2 μm Graded Epitaxial Layer

FIG. 11 is a graph illustrating the drain-source on-resistance Ron (mΩ)as a function of etch variation (μm) for the 0.2 μm graded epitaxiallayer. “0” corresponds to the middle of the 0.2 μm graded epitaxiallayer between the fin and the drift regions. Ron increases significantlywith a 0.1 μm overetch. Referring to FIG. 11 , the Ron upper limit “USL”(upper specification limit) is reached at about 0.05 μm overetch. Thatis, when the etch variation is within the range between ±0.1 μm, theon-resistance value will be outside the upper specification limit.

FIG. 12 is a graph illustrating a threshold voltage Vt (V) as a functionof etch variation (μm) for the 0.2 μm graded epitaxial layer. “0”corresponds to the middle of the 0.2 μm graded epitaxial layer betweenthe fin and the drift regions. Similar to the on-resistance, thethreshold voltage Vt increases significantly with 0.1 μm overetch. Thatis, when the graded doping zone is overetched, the threshold value mayincrease to an unacceptable value. Referring to FIGS. 11 and 12 , anunderetch does provide an improvement in the on-resistance and thresholdvoltage. The underetch also provides an improvement of the maximumelectric field and leakage current, as shown in FIGS. 13 and 14 below.

FIG. 13 is a graph illustrating a maximum electric field (MV/cm) as afunction of etch variation (μm) for the 0.2 μm graded epitaxial layer.The 0.2 μm graded epitaxial layer does provide an improvement in theelectric field with underetch, by allowing the nominal etch to end inthe graded doping layer. The 0.1 μm underetch case is now similar to thenominal case in the first round of simulations, with a slight increasein the electric field because of the additional charge in the gradeddoping layer.

FIG. 14 is a graph illustrating a high-voltage drain leakage currentIdss (A) at 1200V as a function of etch variation (μm) for the 0.2 μmgraded epitaxial layer. Referring to FIG. 14 , the high-voltage drainleakage current Idss remains well controlled with the graded epitaxiallayer. That is, an overetch or underetch does not affect the leakagecurrent.

0.2 μm Fin with 0.3 μm Graded Epitaxial Layer

The inventors conducted a third simulation round using the 0.2 μm finwith a 0.3-μm thick linearly graded epitaxial layer inserted between thefin epitaxial layer and the drift region. In the third simulation round,the nominal etch depth was kept at 0.1 μm below the bottom of the finepitaxial layer, and the results are shown in FIGS. 16 through 19 .

FIG. 15 is a graph illustrating the drain-source on-resistance Ron (mΩ)as a function of etch variation (μm) for the 0.3 μm graded epitaxiallayer. Referring to FIG. 15 , the on-resistance Ron was well controlledfor an underetch in the range of −0.1 μm to zero. Referring to FIG. 15 ,the on-resistance Ron increases by about 10% for the 0.1 μm overetchcondition, which is acceptable and much less than on-resistance observedin the 0.2 μm graded epitaxial layer (see FIG. 11 ) used in the secondset of simulations.

FIG. 16 is a graph illustrating a threshold voltage Vt (V) as a functionof etch variation (μm) for the 0.3 μm graded epitaxial layer. Referringto FIG. 16 , the threshold voltage Vt was well controlled for anunderetch in the range of −0.1 μm to zero. The threshold voltage Vtincrease by about 10% with the 0.1 μm overetch, which is acceptable andmuch less than the threshold voltage Vt illustrated in FIG. 12 for thestructure utilizing 0.2 μm graded epitaxial layer used in the second setof simulations.

FIG. 17 is a graph illustrating an electric field (MV/cm) as a functionof etch variation (μm) for the 0.3 μm graded epitaxial layer. Referringto FIG. 17 , the electric field is higher with the 0.3 μm graded regionthan with the 0.2 μm graded region illustrated in FIG. 13 . At the 0.1underetch condition, the electric field is about 3.15 MV/cm (at theborderline), i.e., the maximum electric field is marginal at the minimumetch depth. The borderline or marginal condition would be improve byadditional optimization, either through a change in the grading orre-centering of the nominal etch depth.

FIG. 18 is a graph illustrating a high-voltage drain leakage currentIdss (A) at 1,200V as a function of etch variation (μm) for the 0.3 μmgraded epitaxial layer. Referring to FIG. 18 , the high-voltage drainleakage current Idss was well controlled over the simulated etch range.

In summary, the inventors have determined that using an abruptfin-epitaxial layer to drift region doping transition, the expectedfin-etch depth process variation will cause unacceptable variations inthe drain-source on-resistance Ron, the threshold voltage Vt, andbreakdown voltage. Inserting a graded-doping zone as a transition layerbetween the fin-epitaxial region and the drift region significantlyimproves the parameter variation with etch process variation. Alinearly-graded, 0.3 μm transition zone achieves good control over thedrain-source on-resistance Ron and Vt variations. The electric field ishigh, and the grading (or etch depth) is optimized by embodiments of thepresent invention to reduce the electric field levels to about 3 MV/cm.

In one embodiment, an existing Silvaco TCAD model for the FET device wasmodified to use In_(0.15)Ga_(0.85)N material in the gate region.Expected polarization charge at the In_(0.15)Ga_(0.85)N/GaN interfacewas calculated using material models and a strain calculation.

Table 1 shows calculated charge components for theIn_(0.15)Ga_(0.85)N/GaN interface.

TABLE 1 In_(0.15)Ga_(0.85)N/GaN Spontaneous, P_(sp)   2.197e13 cm⁻²Piezoelectric, P_(pz) −1.117e13 cm⁻² Net, P_(total)    1.08e13 cm⁻²

It is assumed that this polarization charge occurs on the c-plane, butnot on the channel sidewall (m-plane), following the typical behavior ofIII-N heterointerfaces on these planes.

FIG. 19A is a graph illustrating an effect of no polarization charge onthe current density predicted to result at the c-planeIn_(0.15)Ga_(0.85)N/GaN interface. The graph shows a 2D cross section oftotal current density for the case where polarization is not included.Referring to FIG. 19A, a current 1901 flows from the channel regionbetween the fin (i.e., the channel) and the gate region toward the driftregion without sufficiently spreading horizontally through the interfacebetween the In_(0.15)Ga_(0.85)N gate region and the GaN drift region.FIG. 19B is a graph illustrating an effect of the polarization chargepredicted to result at the c-plane In_(0.15)Ga_(0.85)N/GaN interfaceaccording to some embodiments of the present disclosure. The graph showsa 2D cross section of total current density for the case wherepolarization is included. The net positive fixed charge at the interfacedue to polarization is expected to attract equal and opposite mobilecharge (2D electron gas). The 2DEG at this location results in greatercurrent spreading at the channel opening to the drift layer. Referringto FIG. 19B, the current 1903 flows horizontally along a lateral surfaceof the bottom portion of the gate layer via a two-dimensional electrongas (2DEG), which is induced by polarization of theIn_(0.15)Ga_(0.85)N/GaN interface in the c-plane, then vertically in adirection toward the substrate and the drain metal contact through thedrift region. This can provide significant advantages of smaller devicesizes and lower costs over existing devices that do not includepolarization.

FIG. 20A is a graph illustrating an effect of an electric fieldpredicted to result at the interface between the c-planeIn_(0.15)Ga_(0.85)N gate layer and the GaN drift layer. A relatively lowelectric field is formed uniformly between the gate layer (region) andthe drift layer (region) in an off state. FIG. 20B is a graphillustrating an effect of an electric field predicted to result at thec-plane In_(0.15)Ga_(0.85)N/GaN interface according to some embodimentsof the present disclosure. The graph shows a relatively high electricfield is formed due to the polarization in an off state.

FIG. 20C is a graph illustrating the off-state magnitude of electricfield without polarization 2111 and with polarization 2112. Referring toFIG. 20C, a vertical cutline 2113 is illustrated passing through thenon-channel (p-n junction region). The presence of the 2DEG due topolarization results in high electric field at the interface in theoff-state.

Table 2 illustrates simulated electrical parameters of a baseline GaNFinFET vs. an In_(0.15)Ga_(0.85)N gate FinFET which includespolarization.

TABLE 2 Baseline FinFET InGaN FinFET with polar Ichannel 0.8 0.8Nchannel 1.30E+17 1.30E+17 Graded landing yes yes Fin width (μm) 0.2 0.2Vth (V) 1.23 1.15 IDSS@1200V (A) 8.70E−12 7.10E−12 Max E (MV/cm) 2.924.5 Max E | | (MV/cm) 2.4 2.4 Conductance/unit trench 6.55E−08 6.60E−0.8(S/cm)

As has been demonstrated in FIG. 19A, FIG. 19B, FIGS. 20A through 20C,and Table 2 above, the use of 15% InGaN is shown to be capable ofproviding the benefits expected (lower threshold voltage: Vth 1.15 V vs.1.23V), but with a severe tradeoff of increased E-field (4.5 MV/cm vs.2.92 MV/cm) in the off-state. It suggests using a lower percentage In,which results in lower polarization charge, or even negligiblepolarization. The present inventors will show simulation results for anon-polar InGaN FINFET structure below.

Table 3 illustrates simulated electrical parameters of a baseline GaNFinFET vs. a non-polar InGaN gate FinFET.

TABLE 3 Baseline FinFET InGaN FinFET non-polar Ichannel 0.8 0.8 Nchannel1.30E+17 1.30E+17 Graded landing yes yes Fin width (μm) 0.2 0.2 Vth (V)1.23 1.15 IDSS@1200V (A) 8.70E−12 7.10E−12 Max E (MV/cm) 2.92 2.6 Max E| | (MV/cm) 2.4 2.4 Conductance/unit trench 6.55E−08 6.60E−0.8 (S/cm)

Referring to Table 3, the use of InGaN results in a −0.08V thresholdvoltage shift (1.15V vs. 1.23V) with a low electric field (2.6 MV/cm vs.2.92 MV/cm). The channel doping can be re-tuned to return to thebaseline threshold voltage, resulting in very little electricaldifference between the structures. The advantage for InGaN will be lowertemperature growth and better ohmic contact and p-type doping.

FIG. 21A is a graph illustrating current density through the channel ofa baseline FET. FIG. 21B is a graph illustrating current density throughthe channel of a non-polar FET with a p-type InGaN gate interfacing toan InGaN channel along a non-polar plane. FIG. 21C is a graph of currentdensity through the channel of the baseline FET (curve 2411) comparedwith that of the non-polar FET (curve 2412) at 150 degrees C. In FIG.21C, the current density corresponds to cutline 2110 (shown in FIG. 21A)positioned in the channel. FIG. 21D is a graph of the band diagrams ofthe baseline FET compared with that of the non-polar FET. In FIG. 21D,the band diagrams for the baseline FET (curve 2413) and the non-polarFET (curve 2414) are shown under the gate (non-channel region)corresponding to cutline 2115 (shown in FIG. 21B). The junction 2420 isalso illustrated in FIG. 21D.

According to embodiments of the present invention, FinFETS with p-typegate regions utilizing InGaN (e.g., in place of GaN) are provided. Theutilization of InGaN for the p-type gate material provides a number ofbenefits not available using conventional techniques. For example, someprocess flows described herein utilize the lower growth temperature ofInGaN compared to GaN, which serves to protect the regrowth hardmaskutilized during the regrowth process. Moreover, some embodiments utilizemagnesium doping in which the Mg dopant is shallower in the InGaN layer,resulting in a higher ionization of the dopant at the same temperature.In addition, the lower bandgap of InGaN assists in the formation ofohmic contacts to the p-type region.

Embodiments of the present invention consider the effect of polarizationto achieve a desired trade-off between current spreading and highelectric field, which has been demonstrated.

Additional embodiments are provided below to further illustrate a methodof fabricating vertical fin-based FET devices according to embodimentsof the present invention. Some of the below embodiments focus onfabricating a self-aligned source contact for the vertical fin-based FETdevices.

Additional embodiments of the present invention may provide intermediatesteps following the step 320 of the method 300 illustrated withreference to FIG. 4C. For sake of clarity, the intermediate stage shownin FIG. 4C is generally reproduced in FIG. 22A. Referring to FIG. 22A, avertical fin-based FET device 2200 includes a semiconductor substrate2202, for example, a n+ doped semiconductor substrate. In an embodiment,semiconductor substrate 2202 may include a III-nitride compound, such asn-type GaN. A first semiconductor layer 2204 is epitaxially grown onsemiconductor substrate 2202 at a temperature between 950° C. and 1200°C., preferably between 1000° C. and 1150° C., and more preferably about1100° C. In an embodiment, first semiconductor layer 2204 may include aIII-nitride material, such as n-type GaN. Like the embodimentillustrated with reference to FIGS. 4A-4C, an etch process is performedusing patterned hardmask layer 2210 as a mask to form a plurality ofsemiconductor fins 2206 on first semiconductor layer 2204. Each of theplurality of semiconductor fins 2206 is separated by one of a pluralityof recess regions 2205. In an embodiment, the plurality ofsemiconductors fins 2206 may include III-nitride compound, such asn-type GaN.

In some embodiments, semiconductor substrate 2202 may be heavily dopedwith n-type dopants in a dopant concentration in a range of about 5×10¹⁷atoms/cm³ to about 1×10¹⁹ atoms/cm³ and a resistivity of less than 0.020ohm-cm. In some embodiments, the resistivity of the semiconductorsubstrate 2202, which may be implemented as an n+ doped semiconductorsubstrate, may be from about 0.001 ohm-cm to 0.018 ohm-cm, preferablyless than 0.016 ohm-cm, and more preferably, less than 0.012 ohm-cm. Insome embodiments, first semiconductor layer 2204 is a drift layer havinga thickness of about 12 μm and a dopant concentration in a range ofabout 1×10¹⁶ atoms/cm³. The plurality of semiconductor fins 2206 can becharacterized by uniform doping with n-type dopants of about 1.3×10¹⁷atoms/cm³ and a thickness of about 12 μm. In some embodiments, a gradeddoping layer (not shown in FIG. 22A), such as the graded doping region460 shown in FIG. 4C is disposed between first semiconductor layer 2204and the plurality of semiconductor fins 2206. In some embodiments, eachof the plurality of semiconductor fins 2206 has a width of about 0.2 μm,a height in a range between about 0.7 μm and 0.8 μm, and are spacedapart from each other by a recess region 2205 of about 2.0 μm, i.e., thefin pitch is about 2.0 μm. To provide fins characterized by uniformheight, embodiments of the present invention utilize etch processes thatare characterized by good depth controllability. In some embodiments,each of the plurality of semiconductor fins 2206 may include a metal,such as metal layer 405 shown in FIG. 4C. The metal layer is disposedbetween hardmask layer 2210 and the top of each of the plurality ofsemiconductor fins 2206. For sake of clarity, the metal layer is notshown in FIG. 22A.

In some embodiments, after forming the plurality of recess regions 2205,a cleaning process is carried using a TMAH solution of about 25% byweight, at a temperature of about 85° C., and for a duration of about 5minutes. Thereafter, in an embodiment, a polish etch process isperformed. The polish etch process may include low power Cl-basedchemistry using RIE. In another embodiment, prior to performing acleaning using the TMAH solution, a pre-cleaning such as Piranhacleaning using a H₂SO₄:H₂O in a volume ratio 2:1 for 2 minutes may alsobe performed.

Referring to FIG. 22B, after cleaning is completed, semiconductor gatelayer 2208 is epitaxially regrown in each of the plurality of recessregions 2205 (shown in FIG. 22A). In some embodiments, semiconductorgate layer 2208 may include a p-type GaN material that is grownnon-conformally in the recess regions 2205 at a temperature of about950° C. up to a thickness that is substantially planar to the bottom ofhardmask layer 2210. In some embodiments, the thickness of semiconductorgate layer 2208 is about 840 nm. The p-type GaN layer may be doped withMg with a dopant concentration of about 1×10¹⁹ atoms/cm³. Thereafter, athermal annealing (e.g., a rapid thermal annealing in N₂ at 850° C. for5 minutes) is performed to activate the Mg dopant atoms. The Mg atomsare then activated in the p-type GaN layer in an amount of greater than1% by weight. In some embodiments, a heavily n+ doped layer (not shownin FIG. 22B), such as layer 404 shown in FIG. 4B, may be present betweenthe plurality of semiconductor fins 2206 and hardmask layer 2210.

In some embodiments, a planarization process may be performed onsemiconductor gate layer 2208. In some embodiments, the planarizationprocess includes removing an upper portion of semiconductor gate layer2208 by etching, for example, removing 0.2 μm of the upper portion ofsemiconductor gate layer 2208.

Referring to FIG. 22C, a first dielectric layer 2212 is formed oversemiconductor gate layer 2208 and hardmask layer 2210. In someembodiments, first dielectric layer 2212 is substantially conformal tothe sidewall of the hardmask layer 2210. In an embodiment, firstdielectric layer 2212 has a thickness of approximately 200 nm and mayinclude SiO₂ and be deposited by PECVD at about 300° C. A portion offirst dielectric layer 2212 may be designated as a contact region 2214substantially aligned with each of the plurality of semiconductor fins2206 and a gate region 2216 substantially aligned with the semiconductorgate layer 2208 between fins.

Thereafter, a photoresist layer 2218 that is patterned is formed on thegate region 2216 of first dielectric layer 2212. In some embodiments,the upper surface of photoresist layer 2218 is planar with the uppersurface of contact region 2214 of first dielectric layer 2212. In someembodiments, patterned photoresist layer 2218 is formed and patternedwith well-known photolithography processes to expose contact region 2214of hardmask layer 2210. Next, referring to FIG. 22D, contact region 2214of first dielectric layer 2212 is etched using photoresist layer 2218 asa mask to expose the upper surface of hardmask layer 2210. In someembodiments, contact region 2214 is over etched to extend to apredetermined depth into first dielectric layer 2212 such that the uppersurface of contact region 2214 of first dielectric layer 2212 isdisposed within the thickness of hardmask layer 2210. In an embodiment,the predetermined depth is about 0.25 μm. Thereafter, as shown in FIG.22E, hardmask layer 2210 is etched to expose the upper surface 2220 ofeach of the plurality of semiconductor fins 2206.

Referring to FIG. 22E, photoresist layer 2218 (shown in FIG. 22D) isremoved to expose the upper surface of first dielectric layer 2212 andthe upper surface 2220 of the semiconductor fins 2206. Referring to FIG.22F, a semiconductor source contact portion 2222 is regrown on uppersurface 2220 of each of the plurality of semiconductor fins 2206 andcoupled to each of the plurality of semiconductor fins 2206. In someembodiments, the semiconductor source contact portion 2222 includesn-type GaN with a dopant concentration of about 2×10¹⁷ to 5×10¹⁷atoms/cm³. The regrowth of semiconductor source contact portion 2222 isself-limiting when the semiconductor source contact portion 2222 ischaracterized by a triangular shape. As an example, in a self-limitinggrowth process, the semiconductor source contact portion 2222 can becharacterized by an isosceles triangle shape having a base angle in arange between 58 degrees and 65 degrees in a cross-section view asillustrated in FIG. 22F.

In an embodiment, the semiconductor source contact portion 2222 has aheight of about μm-0.2 μm. In an embodiment, a smooth surface for theregrowth facets can be obtained at a growth temperature in a rangebetween 800° C. and 1150° C. and under a pressure of about 600 mbar withH₂ carrier gas. In an embodiment, the regrowth temperature is in a rangebetween 850° C. and 1100° C., preferably between 900° C. and 1050° C.,and more preferably between about 930° C. and 970° C., e.g., 950° C. inan embodiment.

Thereafter, a source contact structure is formed on first dielectriclayer 2212 and semiconductor source contact portion 2222. In someembodiments, the source contact structure contains multiple (two tofour) metal or metal alloy layers. In an embodiment, the source contactstructure may include a first source metal layer, a second source metallayer, and a third source metal layer. Referring to FIG. 22G, firstsource metal layer 2224 is formed overlying semiconductor source contactportion 2222 and first dielectric layer 2212. In an embodiment, firstsource metal layer 2224 may include titanium having a thickness of about25 nm. Next, second source metal layer 2226 is formed on first sourcemetal layer 2224 and coupled to first source metal layer 2224. In anembodiment, second source metal layer 2226 may include aluminum having athickness of 100 nm. Thereafter, third source metal layer 2228 is formedon second source metal layer 2226 and coupled to second source metallayer 2226. In an embodiment, third source metal layer 2228 may includemolybdenum having a thickness of about 40 nm. In another embodiment,second source metal layer 2226 may include titanium nitride and thirdsource metal layer 2228 may include aluminum. In some embodiments, thirdsource metal layer 2228 is omitted.

Referring to FIG. 22H, a source metal mask layer 2230 is formed on thirdsource metal layer 2228. Source metal mask layer 2230 has opening 2232aligned with gate region 2216. In an embodiment, source metal mask layer2230 is lift-off capable and has a bottom CD of about μm. Thereafter,referring to FIG. 22I, third source metal layer 2228, second sourcemetal layer 2226 and first source metal layer 2224 are etched usingsource metal mask layer 2230 as a mask to expose the upper surface offirst dielectric layer 2212. In an embodiment, the etching process mayinclude Cl-based chemistry using RIE. Then, first dielectric layer 2212is etched away using the source metal mask layer 2230 as a mask toexpose the upper surface of semiconductor gate layer 2208. In anembodiment, etching first dielectric layer 2212 may include F-basedchemistry using RIE.

Referring to FIG. 22J, source metal mask layer 2230 (shown in FIG. 22H)is removed. In an embodiment, a thermal annealing process is performedto provide a stable, low contact resistance contact after removal ofsource metal mask layer 2230. In an embodiment, a rapid thermalannealing (RTA) treatment may be performed in N₂ at 825° C. for 90seconds. After the RTA treatment, the source metal structure willpreferably have a specific resistance of less than about 10⁻⁵ ohm-cm.

Referring to FIGS. 23A-23G, another embodiment of fabricating aself-aligned source contact for the vertical fin-based FET deviceaccording to the present invention is illustrated. As described morefully below, similar processes to those illustrated with reference toFIGS. 22A-22C can be performed to achieve the process stage as shown inFIG. 23A. Specifically, vertical fin-based FET device 2300 includes asemiconductor substrate 2302, which may be an n+ doped semiconductorsubstrate, a first semiconductor layer 2304 epitaxially grown onsemiconductor substrate 2302, and a plurality of semiconductor fins 2306formed on first semiconductor layer 2304. Each of the plurality ofsemiconductor fins 2306 is separated by one of a plurality of recessregions. A semiconductor gate layer 2308 is epitaxially formed in theplurality of recess regions.

Like the embodiment shown in FIG. 22A, hardmask layer 2310 is present ontop of each of the plurality of semiconductor fins 2306. A firstdielectric layer 2312 is formed on semiconductor gate layer 2308 andhardmask layer 2310. In an embodiment, first dielectric layer 2312 issubstantially conformal to the sidewall of the hardmask layer 2310. Aportion of first dielectric layer 2312 may be designated as a contactregion 2314 substantially aligned with each of the plurality ofsemiconductor fins 2306 and a gate region 2316 substantially alignedwith the semiconductor gate layer 2308 between fins. Thereafter, aphotoresist layer 2318 that is patterned is formed on gate region 2316of first dielectric layer 2312. In an embodiment, photoresist layer 2318formed on part of gate region 2316, leaving contact region 2314 to havea width at least three times of the width of each semiconductor fin2306. For example, contact region 2314 having a width of 0.6 μm when thewidth of each of the plurality of semiconductor fins 2306 is 0.2 μm.

Referring to FIG. 23B, first dielectric layer 2312 is etched usingphotoresist layer 2318 as a mask to remove portions of first dielectriclayer 2312 and hardmask layer 2310 and to form a plurality of recessregions 2320. The upper surface 2324 of each of the plurality ofsemiconductor fins 2306 and a portion 2322 of the upper surface ofsemiconductor gate layer 2308 surrounding each of the plurality ofsemiconductor fins 2306 are exposed at the bottom of each of theplurality of recess regions 2320.

Referring to FIG. 23C, photoresist layer 2318 (shown in FIG. 23B) isremoved. Referring to FIG. 23D, a semiconductor source contact portion2326 is epitaxially regrown in each of the plurality of recess regions2320 and coupled to each of the plurality of semiconductor fins 2306. Inan embodiment, semiconductor source contact portion 2326 includes aIII-nitride material, such as n-type GaN with a dopant concentration ofabout 2×10¹⁷ to 5×10¹⁷ atoms/cm³. The regrowth of semiconductor sourcecontact portion 2326 is self-limiting when the source contact portion2326 is characterized by an isosceles trapezoid shape. In an embodiment,semiconductor source contact portion 2326 has a height of about 0.1μm-0.2 μm. In an embodiment, a smooth surface for the regrowth facetscan be obtained at a growth temperature in a range between 800° C. and1150° C. and under a pressure of about 600 mbar with H₂ carrier gas. Inan embodiment, the regrowth temperature is in a range between 850° C.and 1100° C., preferably between 900° C. and 1050° C., and morepreferably between about 930° C. and 970° C., e.g., 950° C. in anembodiment.

Referring to FIG. 23E, first dielectric layer 2312 (shown in FIG. 23D)is removed after regrowth of semiconductor source contact portion 2326to expose the upper surface of semiconductor gate layer 2308. In anembodiment, a wet etch process is performed to remove first dielectriclayer 2312. Referring to FIG. 23F, a source metal mask layer 2328 isformed overlying the exposed upper surface of semiconductor gate layer2308, having an opening 2338 exposing the upper surface of semiconductorsource contact portion 2326. In an embodiment, source metal mask layer2328 is lift-off capable and has a bottom CD of 0.6 μm and a top CD ofμm.

Thereafter, a source contact structure is formed on the exposed uppersurface of semiconductor source contact portion 2326 at a temperature ofabout 25° C.-150° C. In some embodiments, the source contact structurecontains multiple (two to four) metal or metal alloy layers. In anembodiment, the source contact structure may include a first sourcemetal layer 2332, a second source metal layer 2334, and a third sourcemetal layer 2336. Specifically, first source metal layer 2332 is formedoverlying semiconductor source contact portion 2326 and source metalmask layer 2328. In an embodiment, first source metal layer 2332 mayinclude titanium having a thickness of about 25 nm. Next, second sourcemetal layer 2334 is formed on first source metal layer 2332 and coupledto first source metal layer 2332. In an embodiment, second source metallayer 2334 may include aluminum having a thickness of 100 nm.Thereafter, third source metal layer 2336 is formed on second sourcemetal layer 2334 and coupled to second source metal layer 2334. In anembodiment, third source metal layer 2336 may include molybdenum havinga thickness of about 40 nm. In another embodiment, second source metallayer 2334 may include aluminum and third source metal layer 2336 mayinclude titanium nitride. In some embodiments, third source metal layer2336 is omitted.

Referring to FIG. 23G, source metal mask layer 2328 (shown in FIG. 23F)is dissolved to lift off metal layers 2332, 2334 and 2336 depositedthereon, while metal layers 2332, 2334 and 2336 deposited on the uppersurface of semiconductor source contact portion 2326 remain intact. Inan embodiment, the source metal structure has a width of 0.6 μm. In anembodiment, a rapid temperature annealing (RTA) treatment may beperformed in N₂ at 825° C. for 90 seconds. After the RTA treatment, thesource metal structure will preferably have a specific resistance ofless than about 10⁻⁵ ohm-cm.

Referring to FIGS. 24A-24E, another embodiment of fabricating aself-aligned source contact for the vertical fin-based FET device isillustrated. As described more fully below, similar processes to thoseillustrated with reference to FIGS. 22A-22B can be performed to achievethe process stage as shown in FIG. 24A. Specifically, the verticalfin-based FET device 2400 includes a semiconductor substrate 2402, forexample, a n+ doped semiconductor substrate, a first semiconductor layer2404 epitaxially grown on semiconductor substrate 2402, and a pluralityof semiconductor fins 2406 formed on first semiconductor layer 2404.Each of the plurality of semiconductor fins 2406 is separated by one ofa plurality of recess regions. A semiconductor gate layer 2408 isepitaxially formed in the plurality of recess regions. Like theembodiment shown in FIG. 22A, hardmask layer 2410 is present on top ofeach of the plurality of semiconductor fins 2406.

Thereafter, referring to FIG. 24B, hardmask layer 2410 is removed toexposed the upper surface of the plurality of semiconductor fins 2406.In an embodiment, an undoped semiconductor cap layer 2409 is epitaxiallyregrown in at least part of the upper portion of semiconductor gatelayer 2408. In an embodiment, undoped semiconductor cap layer 2409 isepitaxially grown at substantially the central part in the upper portionof semiconductor gate layer 2408 between fins.

Referring to FIG. 24C, a second semiconductor layer 2414 is epitaxiallygrown overlying the plurality of semiconductor fins 2406 andsemiconductor gate layer 2408. In an embodiment, second semiconductorlayer 2414 includes a III-nitride material, such as n-type GaN having afirst dopant concentration. Next, a third semiconductor layer 2415 isepitaxially grown on second semiconductor layer 2414. In an embodiment,third semiconductor layer 2415 includes a III-nitride compound, such asn-type GaN having a second dopant concentration greater than the firstdopant concentration of second semiconductor layer 2414. For clarity ofdescription, a region aligned with each of the plurality ofsemiconductor fins 2406 is designated as contact region 2413, and aregion aligned with semiconductor gate layer 2408 is designated as gateregion 2417. The width of contact region 2413 may be determinedaccording to requirement of the vertical fin-based FET device 2400. Inan embodiment, the width of gate region 2417 at least covers the widthof undoped semiconductor cap layer 2409.

Referring to FIG. 24D, a source metal structure is formed. In someembodiments, the source metal structure contains multiple (two to four)metal or metal alloy layers. Specifically, a first source metal layer2416 is formed on third semiconductor layer 2415. In an embodiment,first source metal layer 2416 may include titanium having a thickness ofabout 25 nm. Next, second source metal layer 2418 is formed on firstsource metal layer 2416 and coupled to first source metal layer 2416. Inan embodiment, second source metal layer 2418 may include aluminumhaving a thickness of 100 nm. Thereafter, third source metal layer 2420is formed on second source metal layer 2418 and coupled to second sourcemetal layer 2418. In an embodiment, third source metal layer 2420 mayinclude molybdenum having a thickness of about 40 nm. In anotherembodiment, second source metal layer 2418 may include titanium nitrideand third source metal layer 2420 may include aluminum. In someembodiments, third source metal layer 2420 is omitted.

Referring to FIG. 24E, a source metal mask layer 2422 is formed on thirdsource metal layer 2420. Source metal mask layer 2422 has opening 2424substantially aligned with gate region 2417. Thereafter, referring toFIG. 24F, source metal layers 2420, 2418 and 2416 are etched usingsource metal mask layer 2422 as a mask to expose the upper surface ofthird semiconductor layer 2415. In an embodiment, the etch process mayinclude Cl-based chemistry using RIE. Next, third and secondsemiconductor layers 2415 and 2414 are etched using source metal masklayer 2422 as a mask to expose the upper surface of semiconductor gatelayer 2408. In an embodiment, the etch process may include Cl-basedchemistry using RIE. Thereafter, a timed etch process is performed usingsource metal mask layer 2422 as a mask to extend into a predetermineddepth in semiconductor gate layer 2408. In an embodiment, the timed etchprocess is performed to eliminate undoped semiconductor cap layer 2409(shown in FIG. 24B).

Referring to FIG. 24G, source metal mask layer 2422 (shown in FIG. 24F)is removed. In an embodiment, a thermal annealing process is performedto provide a stable, low contact resistance contact after removal ofsource metal mask layer 2422. In an embodiment, a rapid thermalannealing (RTA) treatment may be performed in N₂ at 825° C. for 90seconds. After the RTA treatment, the source metal structure will have aspecific resistance of less than about 10⁻⁵ ohm-cm.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present In contrast, when an elementis referred to as being “directly on” or extending “directly onto”another element, there are no intervening elements present. It will alsobe understood that when an element is referred to as being “connected”or “coupled” to another element, it can be directly connected or coupledto the other element or intervening elements may be present. Incontrast, when an element is referred to as being “directly connected”or “directly coupled” to another element, there are no interveningelements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “lateral” or “vertical” may be used herein to describe arelationship of one element, layer or region to another element, layeror region as illustrated in the figures. It will be understood thatthese terms are intended to encompass different orientations of thedevice in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an”, and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”,“comprising”, “includes”, and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Embodiments of the present disclosure are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofthe invention. The thickness of layers and regions in the drawings maybe enlarged relative to other layers and regions for clarity.Additionally, variations from the shapes of the illustrations as aresult, for example, of manufacturing techniques and/or tolerances, areto be expected. Thus, embodiments of the invention should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a discretechange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe invention.

Techniques, methods and devices known to one of ordinary skill in therelevant art may not be discussed in detail, but in situations in whichthese techniques, methods and apparatus apply, these techniques, methodsand apparatus should be considered as part of this specification.Further, similar reference numerals and letters are used to refer tosimilar items in the figures, and once an item is defined in one of thefigures, it will not need to be explained further in the subsequentfigures.

The embodiments disclosed herein are not to be limited in scope by thespecific embodiments described herein. Various modifications of theembodiments of the present invention, in addition to those describedherein, will be apparent to those of ordinary skill in the art from theforegoing description and accompanying drawings. Further, although someof the embodiments of the present invention have been described in thecontext of a particular implementation in a particular environment for aparticular purpose, those of ordinary skill in the art will recognizethat its usefulness is not limited thereto and that the embodiments ofthe present invention can be beneficially implemented in any number ofenvironments for any number of purposes.

What is claimed is:
 1. A transistor comprising: a III-nitride substrate;a first III-nitride layer on the III-nitride substrate, wherein thefirst III-nitride layer is characterized by a first conductivity type; aplurality of III-nitride fins on the first III-nitride layer, whereineach of the plurality of III-nitride fins is separated by one of aplurality of first recess regions and characterized by a fin surface,wherein the plurality of III-nitride fins are characterized by the firstconductivity type; a III-nitride gate layer having a second conductivitytype opposite to the first conductivity type in the plurality of firstrecess regions, wherein a surface of the III-nitride gate layer issubstantially coplanar with the fin surface; and a regrown III-nitridesource contact portion coupled to each of the plurality of III-nitridefins, wherein the regrown III-nitride source contact portion ischaracterized by the first conductivity type.
 2. The transistor of claim1 wherein the III-nitride substrate comprises an n-GaN substrate.
 3. Thetransistor of claim 1 wherein sidewalls of each of the plurality ofIII-nitride fins are aligned with an m-plane and the fin surface isaligned with a c-plane.
 4. The transistor of claim 1 wherein the regrownIII-nitride source contact portion is characterized by a self-limitinggrowth process on top of each of the plurality of III-nitride fins. 5.The transistor of claim 1 wherein the regrown III-nitride source contactportion is characterized by an isosceles triangle shape having a baseangle in a range between 58 degrees and 65 degrees in a cross-sectionview.
 6. The transistor of claim 1 wherein a width of the regrownIII-nitride source contact portion is at least three times of that of awidth of each of the plurality of III-nitride fins.
 7. The transistor ofclaim 1, further comprising a undoped III-nitride cap layer coupled tothe III-nitride gate layer.
 8. The transistor of claim 1 wherein thefirst III-nitride layer and the plurality of III-nitride fins comprisen-GaN epitaxial material.
 9. The transistor of claim 1 wherein the firstIII-nitride layer is characterized by a first dopant concentration andthe plurality of III-nitride fins is characterized by a second dopantconcentration.
 10. The transistor of claim 9 wherein the second dopantconcentration is higher than the first dopant concentration.
 11. Thetransistor of claim 9 wherein the regrown III-nitride source contactportion is characterized by a third dopant concentration that isdifferent from the second dopant concentration.
 12. The transistor ofclaim 1 wherein the III-nitride substrate comprises an n-GaN substrate,the first III-nitride layer and the plurality of III-nitride finscomprise n-GaN epitaxial layers, and the III-nitride gate layercomprises a p-GaN epitaxial layer.
 13. The transistor of claim 1 furthercomprising a graded III-nitride layer disposed between the firstIII-nitride layer and the plurality of III-nitride fins, wherein agraded conductivity of the graded III-nitride layer varies as a functionof distance from the first III-nitride layer.
 14. The transistor ofclaim 1, further comprising a source contact structure coupled to theregrown III-nitride source contact portion.
 15. The transistor of claim14 wherein the source contact structure comprises Ti, Al, and Mopositioned from bottom to top on the regrown III-nitride source contactportion.
 16. The transistor of claim 14 wherein the source contactstructure comprises Ti, TiN, and Al positioned from bottom to top on theregrown III-nitride source contact portion.
 17. The transistor of claim1 further comprising a gate contact structure disposed on theIII-nitride gate layer.